Converting a continuous-time analog signal to a discrete-time digital representation typically requires anti-alias filtering, sampling and quantization. An anti-aliasing filter ensures that analog input signal is properly band-limited prior to sampling. A sampler captures samples of the filtered input signal at discrete time intervals T=1/Fs, where Fs is the sampling frequency. Sampling frequency Fs typically is selected as at least twice the bandwidth of the filtered analog input signal. A quantizer converts the samples to a discrete set of values. Conventional analog-to-digital (A/D) converters typically perform sampling and quantization, whereas separate discrete components or integrated circuits perform anti-aliasing.
Oversampling A/D converters, in contrast, sample an analog input signal at a rate NFs that is many times greater than twice the bandwidth of the analog input signal. An oversampling converter typically includes an anti-alias filter, a sampler and modulator (quantizer), and a digital filter. The sampler and quantizer operate at the elevated rate NFs. The digital filter, typically called a decimator, provides low-pass filtering to suppress signals above Fs/2, and sample-rate reduction to lower the sample rate to the desired rate Fs. As a result of the higher input sampling rate, over-sampling converters have less stringent anti-alias filter requirements than traditional converters. In addition, oversampling converters permit lower quantization noise power, and hence improved signal-to-noise ratio compared to traditional converters.
One key requirement for oversampling A/D converters is low DC offset. If the input to an oversampling A/D converter is zero (e.g., 0 volts), the output of the converter ideally is a digital code corresponding to zero. As a result of component mismatches, however, the output of a real A/D converter to a zero input is a digital code that corresponds to a value other than zero. The magnitude of the converter's input-referred DC offset is the magnitude of the DC input signal that causes the A/D converter to produce a zero output. The DC offset of the converter may vary with time and temperature. This phenomenon typically is called “offset drift.” Another key requirement for oversampling A/D converters is low offset drift with time and temperature.
Previously known techniques have been used to improve the DC offset performance of A/D converters. For example, Donald A. Kerth et al., “An Oversampling Converter for Strain Gauge Transducers,” IEEE J. Solid State Circuits, 27(12): 1689-96 (December 1992), describes an oversampling Δ-Σ A/D converter architecture that uses chopper-stabilized amplifiers to substantially reduce the overall DC offset of the converter. Nevertheless, the non-ideal chopper amplifier switches contribute DC offset and offset drift proportional to the chopper frequency, which corresponds to the relatively high sampling frequency of the Δ-Σ modulator. Although digital calibration techniques may be used to remove residual DC offset, such techniques are ineffective for correcting offset drift. Further, to increase the converter's resolution, the sampling frequency of the Δ-Σ modulator may be increased. Such increases, however, require that the chopper frequency also must increase, which increases residual offset and offset drift.
An improved offset performance A/D converter is described in Damien McCartney et al., “A Low-Noise Low Drift Transducer ADC,” IEEE J. Solid State Circuits, 32(7): 959-967 (July 1997) (“McCartney”). The architecture of the McCartney converter is shown in FIG. 1. Converter 10 includes analog chopper 12, buffer amplifier 14, Δ-Σ modulator 16, digital chopper 18, Sinc3 filter and decimator 20, and FIR filter 22. Analog chopper 12 chops analog input signal VIN with a square wave of frequency fchop. For example, as described by McCartney, if VIN is a differential signal, analog chopper 12 may be implemented as a multiplexer that successively reverses the polarity of VIN. Buffer amplifier 14 isolates the chopped analog input signal from the succeeding switched capacitor circuitry, and may provide adjustable gain. Δ-Σ modulator 16 samples the output of buffer amplifier 14 at a frequency fmod that is much higher than chop frequency fchop, and provides a digital data stream at its output. For example, fmod=2×N×fchop, where N is the oversampling ratio of Δ-Σ modulator 16. Digital chopper 18 is phase-synchronized with analog chopper 12, and chops the digital data output of Δ-Σ modulator 16 to provide a digital data steam at a rate fmod. Sinc3 filter and decimator 20 filter and decimate the output data stream of digital chopper 18 to provide a digital stream x(n) at a rate fmod/N.
If chopper frequency fchop equals fmod/(2×N), then successive samples x(n) provided at the output of Sinc3 filter and decimator 20 are digital representations of the analog signals (VIN+VOS) and (VIN−VOS), where VOS is the input-referred offset of buffer amplifier 14 and Δ-Σ modulator 16. For example, x(n) for n=0, −1, −2, −3, −4, may be expressed as:                                                                         x                ⁡                                  (                  0                  )                                            =                            ⁢                              (                                                                            V                      IN                                        ⁡                                          (                      0                      )                                                        +                                                            V                      OS                                        ⁡                                          (                      0                      )                                                                      )                                                                                                        x                ⁡                                  (                                      -                    1                                    )                                            =                            ⁢                              (                                                                            V                      IN                                        ⁡                                          (                                              -                        1                                            )                                                        +                                                            V                      OS                                        ⁡                                          (                                              -                        1                                            )                                                                      )                                                                                                        x                ⁡                                  (                                      -                    2                                    )                                            =                            ⁢                              (                                                                            V                      IN                                        ⁡                                          (                                              -                        2                                            )                                                        +                                                            V                      OS                                        ⁡                                          (                                              -                        2                                            )                                                                      )                                                                                                        x                ⁡                                  (                                      -                    3                                    )                                            =                            ⁢                              (                                                                            V                      IN                                        ⁡                                          (                                              -                        3                                            )                                                        +                                                            V                      OS                                        ⁡                                          (                                              -                        3                                            )                                                                      )                                                                                                        x                ⁡                                  (                                      -                    4                                    )                                            =                            ⁢                              (                                                                            V                      IN                                        ⁡                                          (                                              -                        4                                            )                                                        +                                                            V                      OS                                        ⁡                                          (                                              -                        4                                            )                                                                      )                                                                        (        1        )            where VIN(n), n=0, =1, =2, =3, =4, . . . , are samples of input signal VIN, and VOS(n), n=0, =1, =2, =3, =4, . . . , are samples of input-referred offset VOS.
FIR filter 22 removes VOS from output x(n) of Sinc3 filter and decimator 20 and provides digital output signal y(n) at rate fchop If FIR filter 22 has L coefficients h(n), n=0, 1, 2, . . . , L−1, output y(n) may be expressed as:                               y          ⁡                      (            n            )                          =                              ∑                          k              =              0                                      L              -              1                                ⁢                                           ⁢                                    h              ⁡                              (                k                )                                      ×                          (                              n                -                k                            )                                                          (        2        )            For example, if L=2, output y(n) may be expressed as:y(n)=h(0)x(n)+h(1)x(n−1)  (3) For n=0, y(0) equals:                     y        ⁡                  (          0          )                                    =                                            h              ⁡                              (                0                )                                      ×                          (              0              )                                +                                    h              ⁡                              (                1                )                                      ×                          (                              -                1                            )                                                                                     ⁢                  (                      4            ⁢                                                   ⁢            a                    )                                                                     =                ⁢                                            h              ⁡                              (                0                )                                      ⁡                          [                                                                    V                    IN                                    ⁡                                      (                    0                    )                                                  +                                                      V                    OS                                    ⁡                                      (                    0                    )                                                              ]                                +                                                               ⁢                  (                      4            ⁢            b                    )                                                                                                ⁢                              h            ⁡                          (              1              )                                [                                                    V                IN                            ⁡                              (                                  -                  1                                )                                      -                                          V                OS                            ⁡                              (                                  -                  1                                )                                              )                                                 If fchop is many times higher than twice the bandwidth of VIN and VOS, thenVIN(0)=VIN(−1)  (5a) VOS(0)=VOS(−1)  (5b) Ideally, y(n) contains no offset VOS, such thaty(n)=VIN(n)  (6) Combining equations (4b), (5) and (6), impulse response coefficients h(0)=+0.5 and h(1)=+0.5.
An alternative embodiment of the converter of FIG. 1 is shown in FIG. 2. Circuit 30 includes excitation source 32, analog chopper 34, sensor 36 and A/D converter 38. Excitation source provides analog excitation input signal EIN, and sensor 36 may be, for example, a resistor bridge strain gauge used in an industrial weigh scale. Analog excitation input signal EIN typically is a DC signal. Analog chopper 34 chops analog excitation input signal EIN, and provides the chopped signal to resistor bridge 36. The analog output of resistor bridge 36 is the input to A/D converter 38. A/D converter 38 includes chop synch 40, which provides analog chopper 34 with a clock signal of the correct polarity and phase to synchronize analog chopper 34 to A/D converter 38. By including sensor 36 in the chop loop, circuit 30 removes offsets in sensor 36 caused by thermal electromotive force (EMF) or leakage current. As described by McCartney, Δ-Σ modulator 16 may be implemented as a 1-bit Δ-Σ modulator, and digital chopper 18 may be implemented as an exclusive-OR gate.
To provide lower quantization error, it may be desirable to implement Δ-Σ modulator 16 as a multi-bit Δ-Σ modulator (i.e., a modulator that provides a multi-bit digital output data stream). Alternatively, it may be desirable to implement modulator 16 using other oversampling quantizer architectures (e.g., successive approximation, flash, or pipelined quantizers) that provide multi-bit digital representations of the signal applied to the quantizer's input. In such multi-bit implementations, digital chopper 18 may not be implemented using a simple exclusive-or gate, but instead requires more complex circuitry.
In various real-world applications, sensors of physical quantities are connected to ADCs. However, due to fluctuations in the input impedance of the ADCs as a result of the signal sampling process, the ADCs must be preceded by relatively high impedance signal processing chains to maintain the accuracy of the ADCs. For high accuracy oversampling converters (i.e., converters that evaluate the input signal at rates much higher than the conversion rate) this presents a difficult requirement.
A variety of solutions have been proposed to achieve relatively high and relatively constant impedance of high accuracy oversampling ADCs. Several of these solutions have included integrated input buffers. However, in each of these proposed solutions that include an input buffer, a compromise is met between DC accuracy and input noise level. For example, low noise level is chosen at the expense of DC accuracy or vice-versa.
It therefore would be desirable to provide an oversampling analog-to-digital converter that has reduced DC offset and offset drift and relatively high and constant input impedance.
It further would be desirable to provide an oversampling analog-to-digital converter that has reduced DC offset and offset drift and relatively high and constant input impedance, but that does not require a digital chopper stage.
It is therefore also desirable to provide an analog-to-digital converter that provides for the use of a low noise external amplifier/buffer while still maintaining exceptional DC accuracy for the overall converter.